In a typical successive approximation register analogue-to-digital conversion (SAR ADC) architecture (as shown in FIG. 1) the input Vin is compared against a digital-to-analogue converter (DAC) output VA using a comparator (3) in several cycles. The input can first go through a sample and hold block (2). The SAR logic (4) executes a search algorithm, typically this is a binary search. In the first cycle the input is compared against the middle of the ADC range. From the comparator output the most significant bit (MSB) can be determined. In the next cycle MSB−1 is determined. A conversion to n bits (7) requires n cycles.
The DAC (5) is typically made with a capacitive DAC. Binary weighted DACs contain capacitances with weight factor 2i for the ith bit. The least significant bit (LSB) has a capacitance C (=20*C) and the MSB has a capacitance 2n−1*C.
In the binary search cycle with a binary weighted capacitive DAC, determining the MSB consumes most energy. The large capacitor controlling the MSB output of the DAC has to be charged to generate the reference level and subsequently discharged if the MSB is 0. With this operation, an energy 2n−1*C*V2/2 is dissipated, and this happens for half of the input samples. Several groups have proposed different configurations which try to recover the energy of this capacitor discharge. In ‘An energy-efficient charge recycling approach for a SAR converter with capacitive DAC’ (Ginsburg et al., Circuits and Systems, 2005, ISCAS2005) the MSB capacitor is split into b−1 binary scaled sub-capacitors. The average switching energy can be reduced by 37% compared to a conventional switching method. The method further uses a charge recycling approach by reconnecting capacitors instead of discharging them.
The power consumption of an ADC can be reduced by improving the operation of the comparator. A technique following this approach is presented in ‘An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes’ (N. Verma et al., Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1196-1205, June 2007). A variety of techniques were employed for minimizing the overall power consumption. Differential binary DACs are used with a standard binary search algorithm. The focus is on the use of a low gain comparator combined with an offset compensating latch. This latch minimizes the gain requirements of the comparator preamplifiers, providing a power reduction of approximately 70% in the preamplifiers.
In ‘Nano-Watt silicon-on-sapphire ADC using 2C-1C capacitor chain’ (Z. Fu et al., Electronics Letters, Vol. 42, No. 6, March 2006) an ultra-low power ADC is presented which combines a 2C-1C capacitor chain implementation and a switched capacitor with cascaded inverter. The latter is chosen as a high-speed and ultra-low power comparator. As a result, the ADC has a power consumption as low as 900 nW at 1.1V power supply and 1.35 μW at 1.5V. One problem with switched capacitor DACs is that of capacitor mismatch. When constructing switched capacitors, process variations such as layer-misalignment or etch variations can cause variations in capacitance values of different capacitors. These variations may only be a few percent of the total capacitance. However, for DACs such as a 10-bit DAC, the largest capacitor is C*29 or 512C and a 5% variation is 26C, many times larger than the smallest capacitors. To improve the matching, a DAC with a thermometer MSB sub-DAC and binary LSB sub-DAC with scrambled thermometer coding is presented in U.S. Pat. No. 6,154,162. This approach is not very profitable for the overall power consumption because the capacitors in the LSB sub-DAC are larger than the capacitors in MSB sub-DAC.